The present invention relates to semiconductor devices, and more specifically, to semiconductor devices including self-aligned contacts (SACs) having a reduced contact resistance.
Semiconductor devices typically include polysilicon gates interposed between a pair of metal contacts. The evolution of semiconductor technology has resulted in decreased gate length scaling and reduced device pitch. As device pitch has decreased, a need to decrease the spacing between metal contacts and the gate electrode has become increasingly important. However, producing small spaces between the gate electrode and the adjacent metal contacts can result in short circuits and other undesirable effects.
One solution to this problem has been to form a gate electrode with self-aligned contacts. The self-aligned contact fabrication process typically includes fully encapsulating the gate electrode with an insulative material (i.e., a gate cap), subsequently forming, in the insulating material, one or more trenches including a barrier layer disposed on the trench sidewalls, and filling the trenches with a metal material to form a metal contact. Accordingly, short-circuit connections between the gate electrode and the metal contacts can be avoided. The barrier layer, however, is susceptible to the formation of one or more irregular features such as raised shoulder portions, for example, when the barrier layer encounters corners formed during the trench formation process. The irregular barrier features can pinch the metal material when filling the contact trenches, in turn causing the formation of one or more voids (e.g., air gaps) in the metal contacts. These voids increase the resistance of the metal contacts, thereby reducing the overall current throughput.